As is known in the art, a voltage regulator is a constant voltage source that adjusts its internal resistance to any occurring changes of load resistance to provide a constant voltage at the regulator output. FIG. 1 is a schematic diagram of a low dropout voltage regulator. The load resistance of the voltage regulator as shown is formed by the parallel combination of the equivalent series resistance RESR of the load capacitor CL and the load resistor RL.
In order to regulate the output voltage resulting from any changes is the load resistor RL, the internal resistance of the voltage regulator must be adjusted to maintain the output voltage VOUT at the desired level. To accomplish this, the output voltage is sensed by the voltage divider formed by the series resistors R1 and R2. As is known, the feedback voltage VFB is the product of the output voltage VOUT and the ratio of the resistor R2 and the sum of the series resistors R1 and R2. An error amplifier receives the feedback voltage VFB and compares it with a reference voltage VREF. The output voltage of the error amplifier AERR is an indication of the error between the feedback voltage VFB and the reference voltage VREF that is applied to gate of the PMOS pass transistor PPASS. The drain-to-source voltage (Vds) and the drain-to-source current (Ids) determine the equivalent internal resistance of the low dropout voltage regulator. As is known, the drain-to-source voltage (Vds) and the drain-to-source current (Ids) are determined by the transconductance of the PMOS pass transistor PPASS and the gate-to-source voltage (Vgs) of the PMOS pass transistor PPASS.
The dropout voltage of the low dropout regulator is normally defined the point at which the drain-to-source voltage (Vds) of the PMOS pass transistor PPASS is not changed when the gate-to-source voltage (Vgs) changes and the PMOS pass transistor PPASS is in saturation.
The size of the PMOS pass transistor PPASS is normally very large to provide the necessary current to the load resistance RL. Further the load capacitance CL and the miller capacitance of the PMOS pass transistor PPASS create a zero the right hand plane that may cause instability in the error amplifier AERR and cause oscillation in the output voltage. To alleviate the instabilities, the compensation capacitor CCOMP is placed between the gate and the drain of the PMOS pass transistor PPASS to shift the zero sufficiently high in frequency to not cause the instabilities.
In the existing low dropout regulators, a line transient at the input voltage terminal VIN may cause the low dropout regulator to go deep into dropout. When the transient is removed from the input terminal VIN, the output of the error amplifier AERR is at a voltage level such that the PMOS pass transistor PPASS is deep into triode region of operation. This causes a very large overshoot voltage level to occur at the output terminal VOUT and across the load capacitance CL and the load resistance RL. The very large overshoot voltage level can cause reliability issues for a load device forming the load capacitance CL and the load resistance RL being powered by low dropout regulator.